Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs

Nowadays when the circuit integration increases, the importance of radiation impact on integrated circuits grows. FPGA circuits are more sensitive to radiation than ASICs. Concurrent error detection (CED) techniques allows faster detection of soft errors (errors which can be corrected by reconfiguration) caused by Single Event Upsets (SEU) [1, 2]. SEUs can also change values in the embedded memory used in the design. These changes are not detectable by off-line tests and some CED techniques have to be used. The probability of a SEU appearing in random access memory (RAM) is described in [3]. Our paper describes a new structure of design for FPGAs which improves reliability parameters and preserves lower area overhead than the classical methods such as duplication or triplication. Our solution assumes the possibility of dynamic reconfiguration of the faulty part. The most important criterion is the speed of the fault detection and the safety of the whole circuit with respect to the surrounding environment. Our methodology enables cooperation between on-line methods and off-line BIST methods for fault detection and localization. Our previous research shows the relation between the area overhead and the fault coverage [4]. Due to small area overhead requirements the fault coverage for most circuit is less than 100%. The fault coverage varies typically from 75% to 95%. To ensure 100% of the fault coverage and to increase reliability parameters, additional methods must be used. There are three basic terms in a field of CED and on-line testing: fault security (FS), self-testing (ST) and totally self-checking (TSC). Detectable faults have to be assorted to four groups A, B, C, D [5] to determine whether the circuit satisfies TSC properties. E.g., the hidden faults belong to the class A. This fault classification can be used to calculate how much the circuit is FS or ST and than calculate TSC properties. Typical results of ST and FS properties are shown in table 1.